Designing Energy-Efficient Fetch Engines

This dissertation evaluates factors that affect the energy-efficiency of the fetch engine in a programmable uniprocessor. The central thesis is that branch prediction is one of the key factors affecting overall processor energy-efficiency. Cooling costs, extending battery life in mobile devices, and reducing utility costs for wall-powered systems, especially data centers are growing concerns. Therefore, better understanding the factors that affect overall processor energy-efficiency has become important for virtually all new processor designs. For a processor to be energy-efficient, power consumption and performance must be balanced. The fetch unit is key to the processor’s execution efficiency because it predicts and fetches all the instructions sent to the execution units. When fetching is stalled, or following an incorrectly predicted path, the rest of the processor is unable to perform useful work (and continues to consume energy). Many different fetch engine designs have been proposed in the research community and understanding how the fetch organization affects the processor’s overall energy-efficiency is essential. For example, previous research has shown that trace caches can yield significant improvement in instruction throughput, but it is unclear whether trace caches are more energy-efficient than traditional instruction caches. Similarly, branch predictors improve fetch bandwidth by increasing instructionlevel parallelism (ILP), but their energy-efficiency has not previously been systematically evaluated.